Electronics Project: Efficient FFT/IFFT implementation technique for OFDM on FPGA

Orthogonal Frequency Division Multiplexing (OFDM) is a special case of multicarrier transmission, where a single data stream is transmitted over a number of lower-rate subcarriers. With the rapid growth of digital wireless communication in recent years, the need for high-speed mobile data transmission has increased. FPGAs have become key components in the implementation of high performance DSP systems.

The objective of this paper is to design and implement a base band OFDM transmitter and receiver on FPGA hardware. This paper concentrates on developing FFT and IFFT. IFFT/ FFT are complex and main blocks of OFDM system also it consumes many resources so new technique is proposed in which FFT/IFFT is implemented in such a way that it consumes very less resources. The work also includes in designing a mapping module, serial to parallel and parallel to serial converter module. All modules are designed using VHDL programming language and implement on Spartan 3e designer kit.

Electronics Project: VLSI Implementation of High Speed and High Resolution FFT Algorithm Based on Radix 2 for DSP Application

This paper concentrates on developing FFT and IFFT. IFFT/ FFT are complex and main blocks of OFDM system also it consumes many resources so new technique is proposed in which FFT/IFFT is implemented in such a way that it consumes very less resources. The work also includes in designing a mapping module, serial to parallel and parallel to serial converter module. All modules are designed using VHDL programming language and implement on Spartan 3e designer kit.

Electronics Project: FPGA IMPLEMENTATION(S) OF A SCALABLE ENCRYPTION ALGORITHM

It was initially designed for software implementations in controllers, smart cards or processors. In this letter, we investigate its performances in recent FPGA devices. For this purpose, a loop architecture of the block cipher is presented. Beyond its low cost performances, a significant advantage of the proposed architecture is its full flexibility for any parameter of the scalable encryption algorithm, taking advantage of generic VHDL coding. The letter also carefully describes the implementation details allowing us to keep small area requirements. Finally, a comparative performance discussion of SEA with the Advanced Encryption Standard Rijndael and ICEBERG (a cipher purposed for efficient FPGA implementations) is proposed. It illustrates the interest of platform/context-oriented block cipher design and, as far as SEA is concerned, its low area requirements and reasonable efficiency. 

Electronics Project: A NEW VLSI ARCHITECTURE OF PARALLEL MULTIPLIER–ACCUMULATOR BASED ON RADIX-2 MODIFIED BOOTH ALGORITHM

     Abstract—In this paper, we proposed a new architecture of multiplier-and-accumulator (MAC) for high-speed arithmetic. By combining multiplication with accumulation and devising a hybrid type of carry save adder (CSA), the performance was improved. Since the accumulator that has the largest delay in MAC was merged into CSA, the overall performance was elevated. The proposed CSA tree uses 1’s-complement-based radix-2 modified Booth’s algorithm (MBA) and has the modified array for the sign extension in order to increase the bit density of the operands. The CSA propagates the carries to the least significant bits of the partial products and generates the least significant bits in advance to decrease the number of the input bits of the final adder. Also, the proposed MAC accumulates the intermediate results in the type of sum and carry bits instead of the output of the final adder, which made it possible to optimize the pipeline scheme to improve the performance. The proposed architecture was synthesized with 250, 180 and 130 m, and 90 nm standard CMOS library. Based on the theoretical and experimental estimation, we analyzed the results such as the amount of hardware resources, delay, and pipelining scheme. We used Sakurai’s alpha power law for the delay modeling. The proposed MAC showed the superior properties to the standard design in many ways and performance twice as much as the previous research in the similar clock frequency. We expect that the proposed MAC can be adapted to various fields requiring high performance such as the signal processing areas. 

Electronics Project: IMPROVEMENT OF THE ORTHOGONAL CODE CONVOLUTION CAPABILITIES USING FPGA IMPLEMENTATION

When data is stored, compressed, or communicated through a media such as cable or air, sources of noise and other parameters such as EMI, crosstalk, and distance can considerably affect the reliability of these data. Error detection and correction techniques are therefore required. Some of those techniques can only detect errors, such as the Cyclic Redundancy Check others are designed to detect as well as correct errors, such as Salomon Codes.However, the existing techniques are not able to achieve high efficiency & to meet bandwidth requirements, especially with the increase in the quantity of data transmitted. Orthogonal Code is one of the codes that can detect errors and correct corrupted data. This project is to enhance the error control capabilities of orthogonal codes by means of Field Programmable Gate Array (FPGA) implementation.

Electronics Project: OPTIMIZED SOFTWARE IMPLEMENTATION OF A FULL-RATE IEEE 802.11A COMPLIANT DIGITAL BASEBAND TRANSMITTER ON A DIGITAL SIGNAL PROCESSOR

     The explosive growth of 802.11-based wireless LANs has attracted interest in providing higher data rates and greater system capacities. Among the IEEE 802.11 standards, the 802.11a standard based on OFDM modulation scheme has been defined to address high - speed and large-system-capacity challenges. Hardware implementations are often used to meet the high-data rate requirements of 802.11a standard. Although software based solutions are more attractive due to the lower cost, shorter development time , and higher flexibility , it is still a challenge to meet the high-data-rate requirements of 802.11a by software. Software - based 802.11a digital baseband transmitter can be designed using Verilog HDL /Matlab.Digital signal processors (DSPs) are a special class of processor optimized for signal-processing applications in communication systems.