Due to the low-cost and
high-data-rate, the popularity of IEEE 802.11-based Wireless Local Area
Networks (WLAN) is growing exponentially. An existing software implementation
for a fully-compliant 802.11a full-rate digital base-band transmitter requires
the use of a 22- processor array running at a 1.0GHz clock frequency to reach
54Mbits/s performance.Digital signal processors (DSPs) are a special class of
processor optimized for signal-processing applications in communication
systems.The 802.11a standard operates in the 5GHz band with possible data rates
of 6, 9, 12, 18, 24, 36, 48, and 54 Mbits/s. The 802.11g standard released in
2003 operates in the 2.4GHz band and supports all the data rates defined in the
802.11a and 802.11b standards. For the higher data rates in 802.11a, the
802.11g standard uses the same OFDM technology in 802.11a, while backward
compatibility is added to support the lower data rates of 802.11b . In this
project, a software-based 802.11a digital base-band processor simulated using
Verilog HDL implementation.
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