Abstract: A configurable multiplier optimized for low power and high
speed operations and which can be configured either for single 16-bit
multiplication operation, single 8-bit multiplication or twin parallel 8-bit
multiplication is designed. The output product can be truncated to further
decrease power consumption and increase speed by sacrificing a bit of output
precision. Furthermore, the proposed multiplier maintains an acceptable output
quality with enough accuracy when truncation is performed. Thus it provides a
flexible arithmetic capacity and a tradeoff between output precision and power
consumption. The approach also dynamically detects the input range of
multipliers and disables the switching operation of the non effective ranges.
Thus the ineffective circuitry can be efficiently deactivated, thereby reducing
power consumption and increasing the speed of operation. Thus the proposed
multiplier outperforms the conventional multiplier in terms of power and speed
efficiencies.
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